To achieve greater processing power, many computer systems now are multiprocessor computer systems that can be scaled to large sizes by adding greater and greater numbers of processors. Such multiprocessor computer systems also typically are designed such that the memory of the computer systems is also allocated to the various processors, which control access to the respective memory blocks with which the processors are respectively associated.
To allow all of the processors of the multiprocessor computer systems to access all of the different memory blocks that are allocated to the various processors and at the same time prevent the occurrence of circumstances in which the accessing of a given memory location by one processor conflicts with the accessing of that memory location by another processor, such computer systems typically employ cache coherency protocols by which the status of the various memory locations is tracked and conflicts are avoided.
Many conventional multiprocessor computer systems employ processors that interact with the memory allocated to those processors by way of a separate memory control device. In at least some such systems, “in main memory” directory-based cache coherency protocols are employed in order to scale the systems. Yet the efficacy of such cache coherency protocols are not easily implemented on computer systems in which the memory controllers are fully integrated (e.g., on a single socket or chip) with the processors controlling those memory controllers, since in such systems the memory controllers can employ protocols that are limited in their scalability.